1. Field of the Invention
This invention relates to an electronic component, terminals of which are formed thickly by electroplating, and to a method of manufacturing such electronic components.
2. Description of the Related Art
In recent years, there have been rapid advances in the miniaturization of portable telephones, transceivers, digital cameras, and other portable equipment. In response to such miniaturization of portable equipment, there have been strong demands for miniaturization of various electronic components which are the constituent components of such equipment (for example, surface acoustic wave (SAW) devices and other piezoelectric devices, integrated circuit (IC) devices, quartz oscillators, drivers, and similar).
WLCSPs (wafer-level chip-size packages) have been developed as technology to satisfy such demands. WLCSP is the latest packing technology for sealing SAW devices and ICs as they exist in the wafer state.
In WLCSP technology, numerous regions intended for chips, in which are provided one or a plurality of functional elements (for example SAW devices), are provided on a wafer, and terminals and wiring are further formed in each of these regions. Next, these regions are sealed as-is with resin or similar in the wafer state, and finally, these regions are cut from the wafer to obtain electronic components (Japanese Patent Laid-open No. 2003-188669).
In many cases, in WLCSP processes the terminals are formed to be thick by electroplating (Japanese Patent Laid-open No. 2003-188669). In order to perform electroplating, electrodes serving as an underlayer is provided, and wiring is connected to these electrodes to supply current from an external power supply.
This wiring for use in plating is unnecessary for the electronic component after separation into a chip. Hence such wiring is removed or cut after the electroplating.
From before the development of WLCSP, technology has existed for the formation by electroplating of thick metal layers on a wafer on which numerous elements are formed, followed by division into separate electronic components. For example, such technology is employed in the manufacture of semiconductor components for TAB (Tape-Automated Bonding) (Japanese Patent Laid-open No. S63-269549).
Bumps (protrusions) are formed by electroplating as bonding terminals on semiconductor components for TAB. FIGS. 1A and 1B are drawings which explains processes for bump formation in a method of manufacture of semiconductor components for TAB. FIG. 1A is a plane view explaining a state in which pads 2 for plating (an underlayer) and wires 4 are formed on the semiconductor substrate 6. On the other hand, FIG. 1B shows in enlargement the region A enclosed by the broken line in FIG. 1A.
In order to form bumps, first an insulating film (not shown) is formed on the semiconductor substrate 6.
Next, the pads 2, and wires 4 connected in common to all the pads 2 on the semiconductor substrate 6, are formed. Here, the principal portions of the wires 4 excluding leader lines 5 are provided on scribe lines.
Next, a photoresist film (not shown) which covers the wires 4 is formed.
Then, using the wires 4 as feed lines, a plating method is employed to form bumps on the pads 2, and the photoresist film is removed.
Thereafter, a dicing saw having a cutting width 8 wider than the width of the wires 4 is used to cut the wires 4 and semiconductor substrate 6 along the above scribe lines, effecting separation into individual semiconductor chips. At this time, each of the bumps connected in common by wires 4 is electrically separated.
According to the method explained referring to FIGS. 1A and 1B, the wires 4, that is, the feed lines, are removed simultaneously with cutting of the semiconductor chips by the dicing saw. Hence this method can be said to be an efficient electronic component manufacturing method which does not require a dedicated process to remove feed lines.
However, this method has the problem that, if the cutting position of the dicing saw (hereafter called the “dicer”) shifts slightly, insulation between bumps, that is, between terminals, cannot be secured.
In general electronic component manufacturing methods, the cutting width 8, that is, the blade width of the dicer, is set slightly wider than the width of the wires, that is, the feed lines (for example, for a feed line width of 40 μm, the cutting width is 50 μm), in order to enable manufacture of as many electronic components as possible from a single wafer (substrate). Hence even if the cutting position of the dicer shifts only slightly from the intended cutting region, feed lines remain uncut.
FIG. 2 is a conceptual diagram explaining a state in which the cutting region 14 has shifted slightly from the intended cutting region.
In addition to the pads 2, function elements (not shown) and wires extending from the pads 2 to the function elements are also formed in the intended chip regions 12, 12′, surrounded by feed lines 10. However, due to complexity of the drawing, these are omitted in FIG. 2.
In FIG. 2, intended cutting regions also are not shown. However, intended cutting regions are regions of width slightly wider than the feed lines 10, and moreover which includes the feed lines 10 in the centers thereof. That is, the intended cutting regions substantially coincide with the regions in which the feed lines 10 are provided.
In the example shown in FIG. 2, the intended cutting regions positioned on the right and left edges and above and below, and the cutting regions 14 cut by the dicer, coincide. Hence in these positions, the feed lines 10 are completely removed by the cutting of the dicer.
On the other hand, in the intended cutting region in the center, the dicer cutting region 14′ is shifted slightly to the left side. As a result, an uncut portion of the feed line 10 remains on the chip separated from the intended chip region 12′ positioned on the right side.
FIG. 3 is a plane view which explains the state of a chip 18 which has been separated from the intended chip region 12′.
As shown in FIG. 3, an uncut portion of a feed line 16 remains extending along the left edge of the chip 18 (in order to distinguish the uncut remaining feed line, the chip edge is shown by a broken line; similarly in other drawings as well).
Each of the plurality of bumps 20′ arranged on the left side of the chip 18 is connected to the uncut remaining feed line 16 by a leader line 5. Hence the bumps 20′ (arranged on the left side of the chip 18) are electrically connected to each other.